The present invention relates to a data line potential setting circuit, and more specifically a data line potential setting circuit for use in an MIS memory circuit, which is composed of insulate gate field effect transistors (which will be shortly referred to as "MIS FET").
In an MIS memory circuit for feeding the data signals to be written, which are generated by a write circuit, through a pair of common data lines to selected one of plural memory cells and for feeding the data signals to be read out, which are then generated from the selected memory cell, through the common data lines to a read out circuit, there exists a relative high parasitic capacity in the paired common data lines so that the signals having a level corresponding to the previous data signals are held in the paired common data lines.
The memory cell selected upon the reading operation establishes such a potential in the paired common data lines as accords to the data signals stored therein. However, a memory cell usually has a reduced drive capacity for a capacitive load because an IC circuit of semiconductor is reduced in size for high integration and for low power consumption.
Therefore, when it is necessary that the potential held at one level in the common data lines be considerably changed to another level by one memory cell, e.g., in case the data signals are written in another memory cell and then are read out of the aforementioned one memory cell, it takes a relatively long time. As a result, the time for reading out the data signals becomes long.
In order to prevent the reduction in the operating rate, it is desired that the respective potentials of the paired data lines be forcibly set in advance in the vicinity of the steady potential which is determined by the memory cells.